What every programmer should know about memory, Part 1 [LWN.net]

kept by elaramirez sep 02

Ulrich Drepper’s LWN series introduces programmers to modern memory hardware, explaining DRAM, caches, NUMA, and how hardware limits affect software performance.

Run AI Models Locally: A New Laptop Era Begins - IEEE Spectrum
The push to run AI models locally is driving the biggest change in laptop architecture in decades, with new NPUs, unified memory, and Microsoft's AI Foundry.
also on AMD, Intel, #hardware
The AI data center deals that no one can verify
AI infrastructure deals lack standardized verification, making headline numbers appear as binding commitments when they are actually contingent options.
also on AMD
Waymo has designed a robocar chip to stay ahead of Tesla
Waymo unveiled a custom 5nm ML ASIC delivering over 1,000 TOPS for ultra‑low latency autonomous driving, built on TSMC’s process and backed by 200 million miles of driving data.
also on Intel, #hardware
Massive demand from AI data centers drives up computer memory prices : NPR
AI-driven demand for memory in data centers has caused RAM prices to double or more, challenging the expectation that tech continually gets cheaper.
also on Intel, #hardware
JP's Website · 2026-08-22 · Why aren't my two Cortex-A9 cores cache coherent?
On a Terasic DE0-Nano-SOC, two Cortex-A9 cores cannot see each other's memory writes despite enabled MMU, caches, and SCU, revealing a cache coherence failure.
also on #linux, #performance, #hardware